This invention relates to memory access circuits and, more particularly, to such circuits which provide for fast, non-contiguous memory retrieval or recording from a single memory concurrently for a number of reading devices.
Traditionally, when there is a desire to access a memory array quickly, designers have either used very fast processors, which are expensive, or they have used hardware assist devices, called DMA's, which access the memory directly and at speeds faster than a processor. DMA's, though, are designed to access data stored contiguously in memory and not to access non-contiguous memory locations. Thus, for DMA's to be effective, data must be stored in memory in a particular manner, which is not always practical.
In addition, if each accessing device were to be operated independently, then each device would require its own DMA, adding expense to memory retrieval or storage process. An example of a memory usage where the data is not stored contiguously for each reading device is our concurrently filed, co-pending patent application Ser. No. 901,003, filed Aug. 27, 1986, which applications have a common assignee and which application is hereby incorporated by reference herein.